1. Field of the Invention
Embodiments of the present invention relate generally to techniques for synchronizing two or more signals and, more particularly, to a technique for synchronizing two or more asynchronous signals without the use of an external system clock.
2. Description of the Related Art
In high speed memory devices, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) devices, it is often desirable to synchronize the timing of certain signals, such as clock signals and data signals, which may be external to the memory devices, with internally generated clock signals, data signals, or other external signals. Various synchronization devices may be implemented to synchronously control a memory device to provide an output signal that is matched in terms of frequency and/or phase to an input signal, which may be a free running external system clock signal, for example.
In certain SDRAM devices, data output may be synchronized using a synchronization circuit, such as a delay lock loop (DLL), which may control the internal clock of the memory device so as to synchronize data output with the rising and/or falling edges of an external system clock. Typically, the DLL circuitry detects a phase difference between a reference clock signal, which may be generated or derived from the external system clock, and a data output signal of the memory device. Based upon the detected phase difference, the DLL circuit may generate a corresponding feedback signal representative of the difference which is used to introduce or remove delay elements as needed in order to attain alignment of the data output signal with the external system clock, thus synchronizing the signals.
While the synchronization of signals under the synchronous control of an external system clock in the manner described above is desirable for preventing erroneous data due to misaligned signals, the power necessary for providing a constant running external system clock signal presents an obstacle for portable electronic devices, which may rely on limited power provided by a battery source for operation, for instance. Such portable electronic devices may also utilize low power circuitry design and low power modes of operation in which an external clock signal may not always be available and, in certain scenarios, may even be undesirable. Furthermore, when viewed in the context of power consumption, the use of an external clock for clocking slower asynchronous signals (e.g., those which pulse only once or a few times over many clock periods (tCK)) may be considered inefficient. However, without a mechanism to bring asynchronous signals into a common clock domain, it cannot be guaranteed that all of the internal logic of the device will operate in the same frequency domain during asynchronous operation, thus increasing the risk of erroneous data inputs or outputs due to signal misalignments.
Embodiments of the present invention may be directed to one or more of the problems set forth above.